By Willy Sansen (auth.), Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto (eds.)
Analog Circuit layout includes the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and helpful layout rules within the zone of analog circuit layout. every one half is gifted through six specialists in that box and state-of-the-art details is shared and overviewed. This ebook is quantity 20 during this winning sequence of Analog Circuit layout, delivering worthy info and ideal overviews of:
Topic 1 : Low Voltage Low strength, chairman: Andrea Baschirotto
Topic 2 : brief variety instant Front-Ends, chairman: Arthur van Roermund
Topic three : strength administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the newest improvement within the box. the educational insurance additionally makes it compatible to be used in a sophisticated layout course.
Read or Download Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC PDF
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Extra info for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC
Depending on the comparator output, the switches c1p or c1n are closed, and the following charge sharing action between CTP , CTN , CMSB and the newly connected CMSB 1 will cause the voltages VQP and VQN to rise or fall. Intuitively one can see that the SAR algorithm at each step uses these pre-charged capacitors to add or subtract a binary scaled-down charge to the initial charge (that represented the sampled input voltage) until the results converges to zero. If too much charge was added during a certain step, the next comparison returns the opposite sign, and in the next step the charge will be subtracted.
IEEE J. SolidState Circuits 38(12), 2031–2039 (2003) 31. K. Gulati, Lee Hae-Seung, A low-power reconfigurable analog-to-digital converter. IEEE J. Solid-State Circuits 36(12), 1900–1911 (2001) 32. C. 5 V 12 b 5 MSample/s pipelined CMOS ADC, in ISSCC Digest Technical Papers, San Francisco, CA, USA, Feb 1996, pp. 314–315 33. D. , 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. SolidState Circuits 41(7), 1589–1595 (2006) 34. S. 7 dB SNR CMOS pipeline ADC. IEEE J. Solid-State Circuits 44(12), 3305–3313 (2009) 35.
Since many stages contribute to the overall input referred noise, a key question is how the input referred noise budget should be distributed across the pipeline to minimize power dissipation. This question was investigated in detail by Cline  and later refined by Chiu . In order to understand the first order result, consider the simplified ADC model in Fig. 6, using a stage gain of two as an example. 3) In words, the noise power of the second stage is divided by 4 when referred to the input, and the third stage noise is divided by 16.